turn Acia into an abstract class so that the 6551 and 6850 ACIAs can reuse code and an unified interface.
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@@ -24,6 +24,7 @@
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package com.loomcom.symon;
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package com.loomcom.symon;
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import com.loomcom.symon.devices.Acia;
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import com.loomcom.symon.devices.Acia;
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import com.loomcom.symon.devices.Acia6551;
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import com.loomcom.symon.devices.Crtc;
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import com.loomcom.symon.devices.Crtc;
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import com.loomcom.symon.devices.Memory;
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import com.loomcom.symon.devices.Memory;
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import com.loomcom.symon.devices.Via;
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import com.loomcom.symon.devices.Via;
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@@ -157,7 +158,7 @@ public class Simulator {
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this.cpu = new Cpu();
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this.cpu = new Cpu();
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this.ram = new Memory(MEMORY_BASE, MEMORY_BASE + MEMORY_SIZE - 1, false);
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this.ram = new Memory(MEMORY_BASE, MEMORY_BASE + MEMORY_SIZE - 1, false);
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this.via = new Via(VIA_BASE);
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this.via = new Via(VIA_BASE);
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this.acia = new Acia(ACIA_BASE);
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this.acia = new Acia6551(ACIA_BASE);
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this.crtc = new Crtc(CRTC_BASE, ram);
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this.crtc = new Crtc(CRTC_BASE, ram);
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bus.addCpu(cpu);
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bus.addCpu(cpu);
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@@ -23,179 +23,47 @@
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package com.loomcom.symon.devices;
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package com.loomcom.symon.devices;
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import com.loomcom.symon.exceptions.MemoryAccessException;
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import com.loomcom.symon.exceptions.MemoryRangeException;
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import com.loomcom.symon.exceptions.MemoryRangeException;
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/**
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/**
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* This is a simulation of the MOS 6551 ACIA, with limited
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* Abstract base class for ACIAS such as the 6551 and 6580
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* functionality. Interrupts are not supported.
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* <p/>
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* Unlike a 16550 UART, the 6551 ACIA has only one-byte transmit and
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* receive buffers. It is the programmer's responsibility to check the
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* status (full or empty) for transmit and receive buffers before
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* writing / reading.
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*/
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*/
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public class Acia extends Device {
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public static final int ACIA_SIZE = 4;
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public abstract class Acia extends Device {
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static final int DATA_REG = 0;
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private String name;
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static final int STAT_REG = 1;
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static final int CMND_REG = 2;
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static final int CTRL_REG = 3;
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/**
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/**
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* Register addresses
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* Register addresses
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*/
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*/
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private int baseAddress;
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int baseAddress;
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/**
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boolean receiveIrqEnabled = false;
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* Registers. These are ignored in the current implementation.
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boolean transmitIrqEnabled = false;
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*/
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boolean overrun = false;
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private int commandRegister;
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private int controlRegister;
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private boolean receiveIrqEnabled = false;
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long lastTxWrite = 0;
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private boolean transmitIrqEnabled = false;
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long lastRxRead = 0;
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private boolean overrun = false;
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int baudRate = 0;
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long baudRateDelay = 0;
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private long lastTxWrite = 0;
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/**
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private long lastRxRead = 0;
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private int baudRate = 0;
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private long baudRateDelay = 0;
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/**
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* Read/Write buffers
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* Read/Write buffers
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*/
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*/
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private int rxChar = 0;
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int rxChar = 0;
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private int txChar = 0;
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int txChar = 0;
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private boolean rxFull = false;
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boolean rxFull = false;
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private boolean txEmpty = true;
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boolean txEmpty = true;
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public Acia(int address) throws MemoryRangeException {
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super(address, address + ACIA_SIZE - 1, "ACIA");
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public Acia(int address, int size, String name) throws MemoryRangeException {
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super(address, address + size - 1, name);
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this.name = name;
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this.baseAddress = address;
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this.baseAddress = address;
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}
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}
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@Override
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public int read(int address) throws MemoryAccessException {
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switch (address) {
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case DATA_REG:
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return rxRead();
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case STAT_REG:
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return statusReg();
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case CMND_REG:
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return commandRegister;
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case CTRL_REG:
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return controlRegister;
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default:
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throw new MemoryAccessException("No register.");
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}
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}
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@Override
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public void write(int address, int data) throws MemoryAccessException {
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switch (address) {
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case 0:
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txWrite(data);
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break;
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case 1:
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reset();
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break;
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case 2:
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setCommandRegister(data);
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break;
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case 3:
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setControlRegister(data);
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break;
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default:
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throw new MemoryAccessException("No register.");
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}
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}
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private void setCommandRegister(int data) {
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commandRegister = data;
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// Bit 1 controls receiver IRQ behavior
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receiveIrqEnabled = (commandRegister & 0x02) == 0;
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// Bits 2 & 3 controls transmit IRQ behavior
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transmitIrqEnabled = (commandRegister & 0x08) == 0 && (commandRegister & 0x04) != 0;
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}
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/**
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* Set the control register and associated state.
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*
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* @param data
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*/
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private void setControlRegister(int data) {
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controlRegister = data;
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// If the value of the data is 0, this is a request to reset,
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// otherwise it's a control update.
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if (data == 0) {
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reset();
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} else {
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// Mask the lower three bits to get the baud rate.
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int baudSelector = data & 0x0f;
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switch (baudSelector) {
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case 0:
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baudRate = 0;
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break;
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case 1:
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baudRate = 50;
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break;
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case 2:
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baudRate = 75;
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break;
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case 3:
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baudRate = 110; // Real rate is actually 109.92
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break;
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case 4:
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baudRate = 135; // Real rate is actually 134.58
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break;
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case 5:
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baudRate = 150;
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break;
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case 6:
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baudRate = 300;
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break;
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case 7:
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baudRate = 600;
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break;
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case 8:
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baudRate = 1200;
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break;
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case 9:
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baudRate = 1800;
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break;
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case 10:
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baudRate = 2400;
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break;
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case 11:
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baudRate = 3600;
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break;
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case 12:
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baudRate = 4800;
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break;
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case 13:
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baudRate = 7200;
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break;
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case 14:
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baudRate = 9600;
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break;
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case 15:
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baudRate = 19200;
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break;
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}
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// Recalculate the baud rate delay.
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baudRateDelay = calculateBaudRateDelay();
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}
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}
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/*
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/*
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* Calculate the delay in nanoseconds between successive read/write operations, based on the
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* Calculate the delay in nanoseconds between successive read/write operations, based on the
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@@ -225,26 +93,17 @@ public class Acia extends Device {
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*/
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*/
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public void setBaudRate(int rate) {
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public void setBaudRate(int rate) {
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this.baudRate = rate;
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this.baudRate = rate;
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this.baudRateDelay = calculateBaudRateDelay();
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}
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}
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/**
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/**
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* @return The contents of the status register.
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* @return The contents of the status register.
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*/
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*/
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public int statusReg() {
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public abstract int statusReg();
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// TODO: Overrun, Parity Error, Framing Error, DTR, DSR, and Interrupt flags.
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int stat = 0;
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if (rxFull && System.nanoTime() >= (lastRxRead + baudRateDelay)) {
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stat |= 0x08;
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}
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if (txEmpty && System.nanoTime() >= (lastTxWrite + baudRateDelay)) {
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stat |= 0x10;
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}
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return stat;
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}
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@Override
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@Override
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public String toString() {
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public String toString() {
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return "ACIA@" + String.format("%04X", baseAddress);
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return name + "@" + String.format("%04X", baseAddress);
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}
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}
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public synchronized int rxRead() {
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public synchronized int rxRead() {
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@@ -293,13 +152,4 @@ public class Acia extends Device {
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return rxFull;
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return rxFull;
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}
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}
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private synchronized void reset() {
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txChar = 0;
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txEmpty = true;
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rxChar = 0;
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rxFull = false;
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receiveIrqEnabled = false;
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transmitIrqEnabled = false;
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}
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}
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}
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@@ -0,0 +1,205 @@
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/*
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* Copyright (c) 2008-2013 Seth J. Morabito <sethm@loomcom.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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package com.loomcom.symon.devices;
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import com.loomcom.symon.exceptions.MemoryAccessException;
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import com.loomcom.symon.exceptions.MemoryRangeException;
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/**
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* This is a simulation of the MOS 6551 ACIA, with limited
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* functionality. Interrupts are not supported.
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* <p/>
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* Unlike a 16550 UART, the 6551 ACIA has only one-byte transmit and
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* receive buffers. It is the programmer's responsibility to check the
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* status (full or empty) for transmit and receive buffers before
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* writing / reading.
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*/
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public class Acia6551 extends Acia {
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public static final int ACIA_SIZE = 4;
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static final int DATA_REG = 0;
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static final int STAT_REG = 1;
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static final int CMND_REG = 2;
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static final int CTRL_REG = 3;
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/**
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* Registers. These are ignored in the current implementation.
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*/
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private int commandRegister;
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private int controlRegister;
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public Acia6551(int address) throws MemoryRangeException {
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super(address, ACIA_SIZE, "ACIA");
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}
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@Override
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public int read(int address) throws MemoryAccessException {
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switch (address) {
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case DATA_REG:
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return rxRead();
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case STAT_REG:
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return statusReg();
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case CMND_REG:
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return commandRegister;
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case CTRL_REG:
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return controlRegister;
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default:
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throw new MemoryAccessException("No register.");
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}
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}
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@Override
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public void write(int address, int data) throws MemoryAccessException {
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switch (address) {
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case 0:
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txWrite(data);
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break;
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case 1:
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reset();
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break;
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case 2:
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setCommandRegister(data);
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break;
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case 3:
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setControlRegister(data);
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break;
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default:
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throw new MemoryAccessException("No register.");
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}
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}
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private void setCommandRegister(int data) {
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commandRegister = data;
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// Bit 1 controls receiver IRQ behavior
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receiveIrqEnabled = (commandRegister & 0x02) == 0;
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// Bits 2 & 3 controls transmit IRQ behavior
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transmitIrqEnabled = (commandRegister & 0x08) == 0 && (commandRegister & 0x04) != 0;
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}
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/**
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* Set the control register and associated state.
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*
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* @param data
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*/
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private void setControlRegister(int data) {
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controlRegister = data;
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int rate = 0;
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// If the value of the data is 0, this is a request to reset,
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// otherwise it's a control update.
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if (data == 0) {
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reset();
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} else {
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// Mask the lower three bits to get the baud rate.
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int baudSelector = data & 0x0f;
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switch (baudSelector) {
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case 0:
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rate = 0;
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break;
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case 1:
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rate = 50;
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break;
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case 2:
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rate = 75;
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break;
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case 3:
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rate = 110; // Real rate is actually 109.92
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break;
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case 4:
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rate = 135; // Real rate is actually 134.58
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break;
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case 5:
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rate = 150;
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break;
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case 6:
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rate = 300;
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break;
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case 7:
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rate = 600;
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break;
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case 8:
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rate = 1200;
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break;
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case 9:
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rate = 1800;
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break;
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case 10:
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rate = 2400;
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break;
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case 11:
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rate = 3600;
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break;
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case 12:
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rate = 4800;
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break;
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case 13:
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rate = 7200;
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break;
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case 14:
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||||||
|
rate = 9600;
|
||||||
|
break;
|
||||||
|
case 15:
|
||||||
|
rate = 19200;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
setBaudRate(rate);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @return The contents of the status register.
|
||||||
|
*/
|
||||||
|
@Override
|
||||||
|
public int statusReg() {
|
||||||
|
// TODO: Overrun, Parity Error, Framing Error, DTR, DSR, and Interrupt flags.
|
||||||
|
int stat = 0;
|
||||||
|
if (rxFull && System.nanoTime() >= (lastRxRead + baudRateDelay)) {
|
||||||
|
stat |= 0x08;
|
||||||
|
}
|
||||||
|
if (txEmpty && System.nanoTime() >= (lastTxWrite + baudRateDelay)) {
|
||||||
|
stat |= 0x10;
|
||||||
|
}
|
||||||
|
return stat;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
private synchronized void reset() {
|
||||||
|
txChar = 0;
|
||||||
|
txEmpty = true;
|
||||||
|
rxChar = 0;
|
||||||
|
rxFull = false;
|
||||||
|
receiveIrqEnabled = false;
|
||||||
|
transmitIrqEnabled = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
@@ -37,7 +37,7 @@ import com.loomcom.symon.exceptions.MemoryRangeException;
|
|||||||
* status (full or empty) for transmit and receive buffers before
|
* status (full or empty) for transmit and receive buffers before
|
||||||
* writing / reading.
|
* writing / reading.
|
||||||
*/
|
*/
|
||||||
public class Acia6850 extends Device {
|
public class Acia6850 extends Acia {
|
||||||
|
|
||||||
public static final int ACIA_SIZE = 2;
|
public static final int ACIA_SIZE = 2;
|
||||||
|
|
||||||
@@ -49,37 +49,14 @@ public class Acia6850 extends Device {
|
|||||||
static final int TX_REG = 1; // write-only
|
static final int TX_REG = 1; // write-only
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Register addresses
|
|
||||||
*/
|
|
||||||
private int baseAddress;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Registers. These are ignored in the current implementation.
|
* Registers. These are ignored in the current implementation.
|
||||||
*/
|
*/
|
||||||
private int commandRegister;
|
private int commandRegister;
|
||||||
|
|
||||||
private boolean receiveIrqEnabled = false;
|
|
||||||
private boolean transmitIrqEnabled = false;
|
|
||||||
private boolean overrun = false;
|
|
||||||
|
|
||||||
private long lastTxWrite = 0;
|
|
||||||
private long lastRxRead = 0;
|
|
||||||
private int baudRate = 0;
|
|
||||||
private long baudRateDelay = 0;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Read/Write buffers
|
|
||||||
*/
|
|
||||||
private int rxChar = 0;
|
|
||||||
private int txChar = 0;
|
|
||||||
|
|
||||||
private boolean rxFull = false;
|
|
||||||
private boolean txEmpty = true;
|
|
||||||
|
|
||||||
public Acia6850(int address) throws MemoryRangeException {
|
public Acia6850(int address) throws MemoryRangeException {
|
||||||
super(address, address + ACIA_SIZE - 1, "ACIA");
|
super(address, ACIA_SIZE, "ACIA6850");
|
||||||
this.baseAddress = address;
|
|
||||||
setBaudRate(2400);
|
setBaudRate(2400);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -126,40 +103,11 @@ public class Acia6850 extends Device {
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Calculate the delay in nanoseconds between successive read/write operations, based on the
|
|
||||||
* configured baud rate.
|
|
||||||
*/
|
|
||||||
private long calculateBaudRateDelay() {
|
|
||||||
if (baudRate > 0) {
|
|
||||||
// TODO: This is a pretty rough approximation based on 8 bits per character,
|
|
||||||
// and 1/baudRate per bit. It could certainly be improved
|
|
||||||
return (long)((1.0 / baudRate) * 1000000000 * 8);
|
|
||||||
} else {
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @return The simulated baud rate in bps.
|
|
||||||
*/
|
|
||||||
public int getBaudRate() {
|
|
||||||
return baudRate;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Set the baud rate of the simulated ACIA.
|
|
||||||
*
|
|
||||||
* @param rate The baud rate in bps. 0 means no simulated baud rate delay.
|
|
||||||
*/
|
|
||||||
public void setBaudRate(int rate) {
|
|
||||||
this.baudRate = rate;
|
|
||||||
this.baudRateDelay = calculateBaudRateDelay();
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @return The contents of the status register.
|
* @return The contents of the status register.
|
||||||
*/
|
*/
|
||||||
|
@Override
|
||||||
public int statusReg() {
|
public int statusReg() {
|
||||||
// TODO: Parity Error, Framing Error, DTR, DSR, and Interrupt flags.
|
// TODO: Parity Error, Framing Error, DTR, DSR, and Interrupt flags.
|
||||||
int stat = 0;
|
int stat = 0;
|
||||||
@@ -176,62 +124,6 @@ public class Acia6850 extends Device {
|
|||||||
return stat;
|
return stat;
|
||||||
}
|
}
|
||||||
|
|
||||||
@Override
|
|
||||||
public String toString() {
|
|
||||||
return "ACIA6850@" + String.format("%04X", baseAddress);
|
|
||||||
}
|
|
||||||
|
|
||||||
public synchronized int rxRead() {
|
|
||||||
lastRxRead = System.nanoTime();
|
|
||||||
rxFull = false;
|
|
||||||
overrun = false;
|
|
||||||
return rxChar;
|
|
||||||
}
|
|
||||||
|
|
||||||
public synchronized void rxWrite(int data) {
|
|
||||||
// when receiving while full: overrun
|
|
||||||
if(rxFull) {
|
|
||||||
overrun = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
rxFull = true;
|
|
||||||
|
|
||||||
if (receiveIrqEnabled) {
|
|
||||||
getBus().assertIrq();
|
|
||||||
}
|
|
||||||
|
|
||||||
rxChar = data;
|
|
||||||
}
|
|
||||||
|
|
||||||
public synchronized int txRead() {
|
|
||||||
txEmpty = true;
|
|
||||||
|
|
||||||
if (transmitIrqEnabled) {
|
|
||||||
getBus().assertIrq();
|
|
||||||
}
|
|
||||||
|
|
||||||
return txChar;
|
|
||||||
}
|
|
||||||
|
|
||||||
public synchronized void txWrite(int data) {
|
|
||||||
lastTxWrite = System.nanoTime();
|
|
||||||
txChar = data;
|
|
||||||
txEmpty = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @return true if there is character data in the TX register.
|
|
||||||
*/
|
|
||||||
public boolean hasTxChar() {
|
|
||||||
return !txEmpty;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @return true if there is character data in the RX register.
|
|
||||||
*/
|
|
||||||
public boolean hasRxChar() {
|
|
||||||
return rxFull;
|
|
||||||
}
|
|
||||||
|
|
||||||
private synchronized void reset() {
|
private synchronized void reset() {
|
||||||
overrun = false;
|
overrun = false;
|
||||||
|
|||||||
@@ -1,6 +1,7 @@
|
|||||||
package com.loomcom.symon;
|
package com.loomcom.symon;
|
||||||
|
|
||||||
import com.loomcom.symon.devices.Acia;
|
import com.loomcom.symon.devices.Acia;
|
||||||
|
import com.loomcom.symon.devices.Acia6551;
|
||||||
import org.junit.Test;
|
import org.junit.Test;
|
||||||
|
|
||||||
import static org.junit.Assert.assertEquals;
|
import static org.junit.Assert.assertEquals;
|
||||||
@@ -12,7 +13,7 @@ public class AciaTest {
|
|||||||
public void shouldTriggerInterruptOnRxFullIfRxIrqEnabled() throws Exception {
|
public void shouldTriggerInterruptOnRxFullIfRxIrqEnabled() throws Exception {
|
||||||
Bus mockBus = mock(Bus.class);
|
Bus mockBus = mock(Bus.class);
|
||||||
|
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
acia.setBus(mockBus);
|
acia.setBus(mockBus);
|
||||||
|
|
||||||
// Disable TX IRQ, Enable RX IRQ
|
// Disable TX IRQ, Enable RX IRQ
|
||||||
@@ -27,7 +28,7 @@ public class AciaTest {
|
|||||||
public void shouldNotTriggerInterruptOnRxFullIfRxIrqNotEnabled() throws Exception {
|
public void shouldNotTriggerInterruptOnRxFullIfRxIrqNotEnabled() throws Exception {
|
||||||
Bus mockBus = mock(Bus.class);
|
Bus mockBus = mock(Bus.class);
|
||||||
|
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
acia.setBus(mockBus);
|
acia.setBus(mockBus);
|
||||||
|
|
||||||
// Disable TX IRQ, Disable RX IRQ
|
// Disable TX IRQ, Disable RX IRQ
|
||||||
@@ -42,7 +43,7 @@ public class AciaTest {
|
|||||||
public void shouldTriggerInterruptOnTxEmptyIfTxIrqEnabled() throws Exception {
|
public void shouldTriggerInterruptOnTxEmptyIfTxIrqEnabled() throws Exception {
|
||||||
Bus mockBus = mock(Bus.class);
|
Bus mockBus = mock(Bus.class);
|
||||||
|
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
acia.setBus(mockBus);
|
acia.setBus(mockBus);
|
||||||
|
|
||||||
// Enable TX IRQ, Disable RX IRQ
|
// Enable TX IRQ, Disable RX IRQ
|
||||||
@@ -63,7 +64,7 @@ public class AciaTest {
|
|||||||
public void shouldNotTriggerInterruptOnTxEmptyIfTxIrqNotEnabled() throws Exception {
|
public void shouldNotTriggerInterruptOnTxEmptyIfTxIrqNotEnabled() throws Exception {
|
||||||
Bus mockBus = mock(Bus.class);
|
Bus mockBus = mock(Bus.class);
|
||||||
|
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
acia.setBus(mockBus);
|
acia.setBus(mockBus);
|
||||||
|
|
||||||
// Disable TX IRQ, Disable RX IRQ
|
// Disable TX IRQ, Disable RX IRQ
|
||||||
@@ -80,14 +81,14 @@ public class AciaTest {
|
|||||||
|
|
||||||
@Test
|
@Test
|
||||||
public void newAciaShouldHaveTxEmptyStatus() throws Exception {
|
public void newAciaShouldHaveTxEmptyStatus() throws Exception {
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
|
|
||||||
assertEquals(0x10, acia.read(0x0001));
|
assertEquals(0x10, acia.read(0x0001));
|
||||||
}
|
}
|
||||||
|
|
||||||
@Test
|
@Test
|
||||||
public void aciaShouldHaveTxEmptyStatusOffIfTxHasData() throws Exception {
|
public void aciaShouldHaveTxEmptyStatusOffIfTxHasData() throws Exception {
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
|
|
||||||
acia.txWrite('a');
|
acia.txWrite('a');
|
||||||
assertEquals(0x00, acia.read(0x0001));
|
assertEquals(0x00, acia.read(0x0001));
|
||||||
@@ -95,7 +96,7 @@ public class AciaTest {
|
|||||||
|
|
||||||
@Test
|
@Test
|
||||||
public void aciaShouldHaveRxFullStatusOffIfRxHasData() throws Exception {
|
public void aciaShouldHaveRxFullStatusOffIfRxHasData() throws Exception {
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
|
|
||||||
acia.rxWrite('a');
|
acia.rxWrite('a');
|
||||||
assertEquals(0x18, acia.read(0x0001));
|
assertEquals(0x18, acia.read(0x0001));
|
||||||
@@ -104,7 +105,7 @@ public class AciaTest {
|
|||||||
@Test
|
@Test
|
||||||
public void aciaShouldHaveTxEmptyAndRxFullStatusOffIfRxAndTxHaveData()
|
public void aciaShouldHaveTxEmptyAndRxFullStatusOffIfRxAndTxHaveData()
|
||||||
throws Exception {
|
throws Exception {
|
||||||
Acia acia = new Acia(0x000);
|
Acia acia = new Acia6551(0x000);
|
||||||
|
|
||||||
acia.rxWrite('a');
|
acia.rxWrite('a');
|
||||||
acia.txWrite('b');
|
acia.txWrite('b');
|
||||||
@@ -115,7 +116,7 @@ public class AciaTest {
|
|||||||
@Test
|
@Test
|
||||||
public void readingBuffersShouldResetStatus()
|
public void readingBuffersShouldResetStatus()
|
||||||
throws Exception {
|
throws Exception {
|
||||||
Acia acia = new Acia(0x0000);
|
Acia acia = new Acia6551(0x0000);
|
||||||
|
|
||||||
acia.rxWrite('a');
|
acia.rxWrite('a');
|
||||||
acia.txWrite('b');
|
acia.txWrite('b');
|
||||||
|
|||||||
Reference in new issue
Block a user