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Start implementation of the VIA6522

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Only PA and PB implemented, not tested
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RuiFPB committed 2026-09-26 19:14:20 +01:00
1 parent 5fa6fa0fc0
commit 558af36cd5
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+64 -3
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src/main/java/com/loomcom/symon/devices/Via6522.java
+64 -3
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@@ -32,18 +32,79 @@ import com.loomcom.symon.exceptions.MemoryRangeException;
public class Via6522 extends Pia {
public static final int VIA_SIZE = 16;
static final int IOB_REG = 0; // Output Register B / Input Register B
static final int IOA_REG = 1; // Output Register A / Input Register A
static final int DDRB_REG = 2; // Data Direction Register B
static final int DDRA_REG = 3; // Data Direction Register A
static final int T1CL_REG = 4; // T1 Low-Order Counter / Latches
static final int T1CH_REG = 5; // T1 High-Order Counter
static final int T1LL_REG = 6; // T1 Low-Order Latches
static final int T1LH_REG = 7; // T1 High-Order Latches
static final int T2CL_REG = 8; // T2 Low-Order Counter / Latches
static final int T2CH_REG = 9; // T2 High-Order Counter
static final int SR_REG = 10; // Shift Register
static final int AuxC_REG = 11; // Auxiliary Control Register
static final int PerC_REG = 12; // Peripheral Control Register
static final int IntF_REG = 13; // Interrupt Flag Register
static final int IntE_REG = 14; // Interrupt Enable Register
static final int IOANH_REG = 15; // Same as Register 1 (IOA), but no Handshake
private int outputRegisterB, inputRegisterB;
private int outputRegisterA, inputRegisterA;
private int dataDirectionB, dataDirectionA;
public Via6522(int address) throws MemoryRangeException {
super(address, address + VIA_SIZE - 1, "MOS 6522 VIA");
}
@Override
public void write(int address, int data) throws MemoryAccessException {
// TODO: Implement write.
switch (address) {
case IOB_REG -> outputRegisterB = data & 0xFF;
case IOA_REG -> outputRegisterA = data & 0xFF;
case DDRB_REG -> dataDirectionB = data & 0xFF;
case DDRA_REG -> dataDirectionA = data & 0xFF;
case IOANH_REG -> outputRegisterA = data & 0xFF;
default -> throw new MemoryAccessException("No Register or Not Implemented!");
}
}
@Override
public int read(int address, boolean cpuAccess) throws MemoryAccessException {
// TODO: Implement read.
return 0;
return switch (address) {
case IOB_REG -> pbRead(cpuAccess);
case IOA_REG -> paRead(cpuAccess);
case DDRB_REG -> dataDirectionB;
case DDRA_REG -> dataDirectionA;
case IOANH_REG -> paRead(cpuAccess);
default -> throw new MemoryAccessException("No Register or Not Implemented!");
};
}
public void setInputRegisterB(int data) {
inputRegisterB = data & 0xFF;
}
public void setInputRegisterA(int data) {
inputRegisterA = data & 0xFF;
}
public int getOutputRegisterB() {
return outputRegisterB;
}
public int getOutputRegisterA() {
return outputRegisterA;
}
private int pbRead(boolean cpuAccess) {
// Return bits of output register where DDRB is 1 and input register where DDRB is 0
return (outputRegisterB & dataDirectionB) | (inputRegisterB & ~dataDirectionB);
}
private int paRead(boolean cpuAccess) {
// Return bits of output register where DDRB is 1 and input register where DDRB is 0
return (outputRegisterA & dataDirectionA) | (inputRegisterA & ~dataDirectionA);
}
}