Add NMI flag to CPU

This commit is contained in:
Seth Morabito committed 2014-01-25 20:02:17 -08:00
1 parent 0c5035fc56
commit b6cc480919
3 files changed
+62 -20

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+16 -4
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@@ -151,15 +151,27 @@ public class Bus {
throw new MemoryAccessException("Bus write failed. No device at address " + String.format("$%04X", address)); throw new MemoryAccessException("Bus write failed. No device at address " + String.format("$%04X", address));
} }
public void assertInterrupt() { public void assertIrq() {
if (cpu != null) { if (cpu != null) {
cpu.assertInterrupt(); cpu.assertIrq();
} }
} }
public void clearInterrupt() { public void clearIrq() {
if (cpu != null) { if (cpu != null) {
cpu.clearInterrupt(); cpu.clearIrq();
}
}
public void assertNmi() {
if (cpu != null) {
cpu.assertNmi();
}
}
public void clearNmi() {
if (cpu != null) {
cpu.clearNmi();
} }
} }
+24 -10
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@@ -133,7 +133,7 @@ public class Cpu implements InstructionTable {
state.overflowFlag = false; state.overflowFlag = false;
state.negativeFlag = false; state.negativeFlag = false;
state.interruptAsserted = false; state.irqAsserted = false;
// Clear illegal opcode trap. // Clear illegal opcode trap.
state.opTrap = false; state.opTrap = false;
@@ -154,7 +154,7 @@ public class Cpu implements InstructionTable {
} }
/** /**
* Performs an individual machine cycle. * Performs an individual instruction cycle.
*/ */
public void step() throws MemoryAccessException { public void step() throws MemoryAccessException {
// Store the address from which the IR was read, for debugging // Store the address from which the IR was read, for debugging
@@ -1168,15 +1168,29 @@ public class Cpu implements InstructionTable {
/** /**
* Simulate transition from logic-high to logic-low on the INT line. * Simulate transition from logic-high to logic-low on the INT line.
*/ */
public void assertInterrupt() { public void assertIrq() {
state.interruptAsserted = true; state.irqAsserted = true;
} }
/** /**
* Simulate transition from logic-low to logic-high of the INT line. * Simulate transition from logic-low to logic-high of the INT line.
*/ */
public void clearInterrupt() { public void clearIrq() {
state.interruptAsserted = false; state.irqAsserted = false;
}
/**
* Simulate transition from logic-high to logic-low on the NMI line.
*/
public void assertNmi() {
state.nmiAsserted = true;
}
/**
* Simulate transition from logic-low to logic-high of the NMI line.
*/
public void clearNmi() {
state.nmiAsserted = false;
} }
/** /**
@@ -1323,8 +1337,8 @@ public class Cpu implements InstructionTable {
public int[] args = new int[2]; public int[] args = new int[2];
public int instSize; public int instSize;
public boolean opTrap; public boolean opTrap;
/* True if the INT line was held low */ public boolean irqAsserted;
public boolean interruptAsserted; public boolean nmiAsserted;
/* Status Flag Register bits */ /* Status Flag Register bits */
public boolean carryFlag; public boolean carryFlag;
@@ -1361,7 +1375,7 @@ public class Cpu implements InstructionTable {
this.args[1] = s.args[1]; this.args[1] = s.args[1];
this.instSize = s.instSize; this.instSize = s.instSize;
this.opTrap = s.opTrap; this.opTrap = s.opTrap;
this.interruptAsserted = s.interruptAsserted; this.irqAsserted = s.irqAsserted;
this.carryFlag = s.carryFlag; this.carryFlag = s.carryFlag;
this.negativeFlag = s.negativeFlag; this.negativeFlag = s.negativeFlag;
this.zeroFlag = s.zeroFlag; this.zeroFlag = s.zeroFlag;
@@ -1370,7 +1384,7 @@ public class Cpu implements InstructionTable {
this.breakFlag = s.breakFlag; this.breakFlag = s.breakFlag;
this.overflowFlag = s.overflowFlag; this.overflowFlag = s.overflowFlag;
this.stepCounter = s.stepCounter; this.stepCounter = s.stepCounter;
} }
/** /**
* Returns a string formatted for the trace log. * Returns a string formatted for the trace log.
+22 -6
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@@ -119,20 +119,36 @@ public class BusTest extends TestCase {
assertTrue("Address space should have been complete!", b.isComplete()); assertTrue("Address space should have been complete!", b.isComplete());
} }
public void testSetAndClearInterrupt() throws Exception { public void testSetAndClearIrq() throws Exception {
Bus b = new Bus(0x0000, 0xffff); Bus b = new Bus(0x0000, 0xffff);
Cpu c = new Cpu(); Cpu c = new Cpu();
b.addCpu(c); b.addCpu(c);
assertFalse(c.getCpuState().interruptAsserted); assertFalse(c.getCpuState().irqAsserted);
b.assertInterrupt(); b.assertIrq();
assertTrue(c.getCpuState().interruptAsserted); assertTrue(c.getCpuState().irqAsserted);
b.clearInterrupt(); b.clearIrq();
assertFalse(c.getCpuState().interruptAsserted); assertFalse(c.getCpuState().irqAsserted);
}
public void testSetAndClearNmi() throws Exception {
Bus b = new Bus(0x0000, 0xffff);
Cpu c = new Cpu();
b.addCpu(c);
assertFalse(c.getCpuState().nmiAsserted);
b.assertNmi();
assertTrue(c.getCpuState().nmiAsserted);
b.clearNmi();
assertFalse(c.getCpuState().nmiAsserted);
} }
} }