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@@ -161,10 +161,8 @@ public class Cpu implements InstructionTable {
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irAddressMode = (state.ir >> 2) & 0x07;
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irOpMode = state.ir & 0x03;
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// Increment PC
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incrementPC();
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// Clear the illegal opcode trap.
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clearOpTrap();
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// Decode the instruction and operands
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@@ -175,7 +173,6 @@ public class Cpu implements InstructionTable {
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incrementPC();
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}
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// Increment step counter
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state.stepCounter++;
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// Get the data from the effective address (if any)
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@@ -412,18 +409,17 @@ public class Cpu implements InstructionTable {
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}
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state.pc = address(bus.read(lo), bus.read(hi));
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/* TODO: For accuracy, allow a flag to enable broken behavior
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* of early 6502s:
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*
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* "An original 6502 has does not correctly fetch the target
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* address if the indirect vector falls on a page boundary
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* (e.g. $xxFF where xx is and value from $00 to $FF). In this
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* case fetches the LSB from $xxFF as expected but takes the MSB
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* from $xx00. This is fixed in some later chips like the 65SC02
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* so for compatibility always ensure the indirect vector is not
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* at the end of the page."
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* (http://www.obelisk.demon.co.uk/6502/reference.html#JMP)
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*/
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/* TODO: For accuracy, allow a flag to enable broken behavior of early 6502s:
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*
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* "An original 6502 has does not correctly fetch the target
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* address if the indirect vector falls on a page boundary
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* (e.g. $xxFF where xx is and value from $00 to $FF). In this
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* case fetches the LSB from $xxFF as expected but takes the MSB
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* from $xx00. This is fixed in some later chips like the 65SC02
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* so for compatibility always ensure the indirect vector is not
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* at the end of the page."
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* (http://www.obelisk.demon.co.uk/6502/reference.html#JMP)
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*/
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break;
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@@ -724,6 +720,7 @@ public class Cpu implements InstructionTable {
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break;
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/** Unimplemented Instructions ****************************************/
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// TODO: Create a flag to enable highly-accurate emulation of unimplemented instructions.
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default:
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setOpTrap();
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break;
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