Commit Graph
7 Commits
Author SHA1 Message Date
Tim Allen b5a470d3ba Make the Processor Status register match a real 6502 at power-on.
When describing the CPU's reset pin, the W65C02S data sheet says:

> All Registers are initialized by software except the Decimal and Interrupt
> disable mode select bits of the Processor Status Register (P) are initialized
> by hardware.

It then has a diagram of the power-on state of the processor status register:

>     7 6 5 4 3 2 1 0
>     * * 1 1 0 1 * *
>     N V - B D I Z C
>
> * = software initialized

Confusingly the text indicates that only the D and I flags are initialised by
hardware, while the diagram indicates that the B flag is initialised too.

Meanwhile, https://www.nesdev.org/wiki/CPU_power_up_state says that
the power-on state of the NES CPU is $34 (exactly matching the diagram above)
but https://www.nesdev.org/wiki/Status_flags#The_B_flag says that the B flag
does not physically exist within P register, it's only relevant in the copy
of P that gets pushed to the stack by BRK (set), PHP (set), or an interrupt
signal (cleared).

As a result, the most sensible power-on state for the processor status register
is with the "interrupt disable" flag set and everything else cleared.
2023-02-03 18:16:57 +11:00
Matt Harlum 96819f1bf7 Issue #16: Memory window should not reset device registers 2017-05-26 17:01:41 +10:00
Maik Merten 52f4e9a00f enforce that the address range of devices falls within the address range of the bus. Turned out that the CPU tests instantiate memory with the last parameter as memory size, not end address (fixed now). Also make sure that the address lookup array takes the offset caused by non-zero starting addresses into account. 2014-07-25 21:24:16 +02:00
Seth Morabito bc3de80892 Execution Trace Log
Introduces an execution trace window that will keep track of the most
recent 10000 execution steps. I'm not entirely happy with the
implementation, yet.
2012-12-09 17:04:31 -08:00
Seth Morabito 2ebdd254b3 Work In Progress: CPU behavior, UI changes
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:

1. Allow loading of 16KB ROM files at address $C000 at run-time, not
   just at startup. See the "Load ROM..." File menu item.

2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
   implementation can match the behavior of either an early NMOS 6502, late
   NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
   far.

3. Adds a completely bogus implementation of the 6522 VIA (it
   does absolutely nothing right now).

4. Changes the address of the ACIA in the simulated system to match a
   real hardware implementation I put together.
2012-11-25 22:49:21 -08:00
Seth J. Morabito 00ab8cd9ff Simulator is just about ready for real-world testing now. Added a simulated
MOS6551 ACIA at address $C000 which does buffered input and output via the
console. Updated the README with a bit more documentation, and bumped the
version number to 0.1 because I'm impatient.
2010-01-20 18:19:39 -08:00
Seth Morabito f174f0312f * Correct implementation of Indirect Indexed and Indexed Indirect addressing modes.
* Unit tests for Indirect Indexed and Indexed Indirect.
* Updated copyright dates.
* Started moving to JUnit 4.
2010-01-15 08:20:03 +00:00