This change adds a new "Step Over" button, which is enabled
when a "JSR" (Jump to Subroutine) instruction is encountered
while stepping through execution one instruction at a time.
Pressing "Step Over" will continue running instructions until a
corresponding "RTS" (Return from Subroutine) is encountered.
While stepping over a subroutine, the call stack depth is tracked
in an attempt to halt only when the *correct* RTS is encountered.
In other words, it should skip over other subroutines nested
inside the call you want to step over:
```
JSR A # Step over here...
...
JSR B
...
RTS # Returns from 'B', doesn't halt
...
RTS # Returns from 'A', halts after return
```
Implements feature request #18.
So far as I can tell, ever since the first version of the ACIA emulation in
Symon, writing 0x00 to the control register has been interpreted as a request
to reset, rather than to actually set the control register to 0x00. This is
strange for a number of reasons:
- All-zeros is actually a very sensible value for the control register, and
is in fact the hardware-reset default.
- I can't find any description of such behaviour in the 6551, W65C51S, or
W65C51N data sheets.
- The 6551 already has a way to trigger "program reset" by writing to the
status register.
So I've removed that quirk, and writing to the control register now just
writes to the control register and nothing else.
The only description of the effects of "program reset" in the original MOS
datasheet is in the section for each register. The W65C51S and W65C51N
datasheets have a heading "PROGRAM RESET OPERATION", but it amounts to:
- internal registers are modified as described in the section for each register
- changes to the DTR, DCD, and DSR pins which Symon does not emulate
- the overrun flag is cleared
...which is what this new implementation does.
It would make *sense* for the reset to do things like "cancel transmission or
reception in progress" and stop asserting an interrupt, as the old code did,
but I can't find any evidence of such behaviour in the datasheets.
* Fix ACIA6850 Interrupt behavior, Interrupt should be cleared on status register read.
* Remove unneeded cpuAccess if statement from Acia6850 write that was preventing build completion
* Fix ACIA6850 Tests so they run.
There are still active users on Java 1.7, so building with Java 8
was a no-no. This change reverts the recent migration to Java 8,
allowing JDK 1.7 to compile the code.
This means, at least for the time being, no more Lambda expressions
(Boooooooooooooooo!!)
- IR field in status panel now correctly displays the next instruction
to be executed, instead of the instruction that was just executed.
- Switched from built-in Java util logger to Logback
- Updated all copyright strings to 2016
- Added more CRTC information to the README file.
- Added unit tests for the CRTC.
- Implemented register read for cursor position in the CRTC.
- Bundling a new version of jterminal that has correct backspace
behavior.
The simulator now passes Klaus Dormann's 6502 Functional Test suite for
the first time.
Bug Fixes:
- PHP was not correctly setting the Break bit on the stack copy of the
processor status, so subsequent PLA's would not set the Break status
flag.
- The CPU had swapped NMI and IRQ reset vectors, so RTI was failing.
- BRK was pushing PC + 2 onto the stack, instead of PC + 1
- (Zero Page,X) addressing mode did not correctly wrap on zero page
boundaries.
- The instruction table used for disassembly had addressing modes
of LDA $B9 and $BD reversed. This did not affect behavior, only
disassembly of these instructions.
Other:
- Updated copyright date for 2013.
- Started migrating old JUnit 3 style tests to JUnit 4 annotations.
- The UI layout has changed, and will likely change again in the future.
- Symon can now re-load ROM images from the File menu, under "Load ROM..."
- Font size can be changed under the "View" menu
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:
1. Allow loading of 16KB ROM files at address $C000 at run-time, not
just at startup. See the "Load ROM..." File menu item.
2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
implementation can match the behavior of either an early NMOS 6502, late
NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
far.
3. Adds a completely bogus implementation of the 6522 VIA (it
does absolutely nothing right now).
4. Changes the address of the ACIA in the simulated system to match a
real hardware implementation I put together.
Seth Morabito