Introduces several changes requested by Mario Keller. The simulator now has a variable step count that can be selected by a drop-down box on the main window. This change also displays ASCII characters in the Memory window.
The simulator now passes Klaus Dormann's 6502 Functional Test suite for
the first time.
Bug Fixes:
- PHP was not correctly setting the Break bit on the stack copy of the
processor status, so subsequent PLA's would not set the Break status
flag.
- The CPU had swapped NMI and IRQ reset vectors, so RTI was failing.
- BRK was pushing PC + 2 onto the stack, instead of PC + 1
- (Zero Page,X) addressing mode did not correctly wrap on zero page
boundaries.
- The instruction table used for disassembly had addressing modes
of LDA $B9 and $BD reversed. This did not affect behavior, only
disassembly of these instructions.
Other:
- Updated copyright date for 2013.
- Started migrating old JUnit 3 style tests to JUnit 4 annotations.
- If a default ROM image ("rom.bin") isn't available at startup, the
simulator will now create and load a 16KB R/W memory at the ROM
location, so resets will work even without a ROM loaded.
- Cleaned up the way simulator UI state is updated when the run loop
exits.
I was alarmed to discover just how slow `String.format()` is for doing
integer to hex conversions. Now that a trace window has been added to
Symon, it became especially clear that I needed a more efficient way to
handle it.
I looked into using `Integer.toHexString()`, but I would have had to
wrap it to do zero-padding, so I decided to just bite the bullet and do
my own with a lookup table. The implementation in `HexUtil` is just as
fast as `Integer.toHexString()`, but also zero-pads appropriately.
Combined with Java's `+` String concatenation, it seems perfectly
adequate.
For yet better performance with the trace window, it would make a lot of
sense to special-case stepping so that it just pops the top line off the
log, and appends to the bottom, rather than re-stringifying the entire
trace log each time. This will be a future enhancement.
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:
1. Allow loading of 16KB ROM files at address $C000 at run-time, not
just at startup. See the "Load ROM..." File menu item.
2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
implementation can match the behavior of either an early NMOS 6502, late
NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
far.
3. Adds a completely bogus implementation of the 6522 VIA (it
does absolutely nothing right now).
4. Changes the address of the ACIA in the simulated system to match a
real hardware implementation I put together.
MOS6551 ACIA at address $C000 which does buffered input and output via the
console. Updated the README with a bit more documentation, and bumped the
version number to 0.1 because I'm impatient.
Seth Morabito