When describing the CPU's reset pin, the W65C02S data sheet says:
> All Registers are initialized by software except the Decimal and Interrupt
> disable mode select bits of the Processor Status Register (P) are initialized
> by hardware.
It then has a diagram of the power-on state of the processor status register:
> 7 6 5 4 3 2 1 0
> * * 1 1 0 1 * *
> N V - B D I Z C
>
> * = software initialized
Confusingly the text indicates that only the D and I flags are initialised by
hardware, while the diagram indicates that the B flag is initialised too.
Meanwhile, https://www.nesdev.org/wiki/CPU_power_up_state says that
the power-on state of the NES CPU is $34 (exactly matching the diagram above)
but https://www.nesdev.org/wiki/Status_flags#The_B_flag says that the B flag
does not physically exist within P register, it's only relevant in the copy
of P that gets pushed to the stack by BRK (set), PHP (set), or an interrupt
signal (cleared).
As a result, the most sensible power-on state for the processor status register
is with the "interrupt disable" flag set and everything else cleared.
The simulator now passes Klaus Dormann's 6502 Functional Test suite for
the first time.
Bug Fixes:
- PHP was not correctly setting the Break bit on the stack copy of the
processor status, so subsequent PLA's would not set the Break status
flag.
- The CPU had swapped NMI and IRQ reset vectors, so RTI was failing.
- BRK was pushing PC + 2 onto the stack, instead of PC + 1
- (Zero Page,X) addressing mode did not correctly wrap on zero page
boundaries.
- The instruction table used for disassembly had addressing modes
of LDA $B9 and $BD reversed. This did not affect behavior, only
disassembly of these instructions.
Other:
- Updated copyright date for 2013.
- Started migrating old JUnit 3 style tests to JUnit 4 annotations.
Introduces an execution trace window that will keep track of the most
recent 10000 execution steps. I'm not entirely happy with the
implementation, yet.
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:
1. Allow loading of 16KB ROM files at address $C000 at run-time, not
just at startup. See the "Load ROM..." File menu item.
2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
implementation can match the behavior of either an early NMOS 6502, late
NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
far.
3. Adds a completely bogus implementation of the 6522 VIA (it
does absolutely nothing right now).
4. Changes the address of the ACIA in the simulated system to match a
real hardware implementation I put together.
- Removed the CommandParser class entirely, as the weird dependency between
Simulator and CommandParser never made me comfortable.
- Added a Command inner class to Simulator that handles some of the
command line tokenizing.
Tim Allen