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### IntelliJ IDEA ###
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out/
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!**/src/main/**/out/
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!**/src/test/**/out/
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.kotlin
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### Eclipse ###
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.apt_generated
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.classpath
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.factorypath
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.project
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.settings
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.springBeans
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.sts4-cache
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bin/
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!**/src/main/**/bin/
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!**/src/test/**/bin/
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### NetBeans ###
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/nbproject/private/
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/nbbuild/
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/dist/
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/nbdist/
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/.nb-gradle/
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### VS Code ###
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.vscode/
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### Mac OS ###
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.DS_Store
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.idea/
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symon*.jar
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*.bin
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*.map
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OUTPUT := example.bin
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TARGET_CPU := 65c02
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MEM_MAP_FILE := $(OUTPUT:.bin=.map)
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# Tool list
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CC65 := cc65
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CA65 := ca65
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LD65 := ld65
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CL65 := cl65
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# Searches directly under src and one level under. If a file is under 2 folders
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#such as src/math/float/types.s, either one more level needs to be added, or
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#switch these to a shell find $(shell find src -name '*.s')
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C_SOURCES := $(wildcard src/*.c) $(wildcard src/*/*.s)
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ASM_SOURCES := $(wildcard src/*.s) $(wildcard src/*/*.s)
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OBJECTS := $(ASM_SOURCES:.s=.o)
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.PHONY: all clean
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all: $(OUTPUT)
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$(OUTPUT): $(C_SOURCES) $(ASM_SOURCES)
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@mkdir -p $(dir $@)
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$(CL65) -t none --cpu $(TARGET_CPU) -C computer.cfg -m $(MEM_MAP_FILE) -O -o $@ $^
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clean:
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rm -f $(OBJECTS)
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rm -f $(OUTPUT)
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# 65C02 Assembly Project Template
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This template is based on the memory map for Mike42's computer/board. [Github](https://github.com/mike42/6502-computer/)
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# Physical Memory configuration
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MEMORY {
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ZP: start = $00, size = $0100, type = rw, file = "";
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RAM: start = $0200, size = $7d00, type = rw, file = "";
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PRG: start = $C000, size = $4000, type = ro, file = %O, fill = yes, fillval = $00;
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}
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# In-Code Segment separators
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SEGMENTS {
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ZEROPAGE: load = ZP, type = zp;
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BSS: load = RAM, type = bss;
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CODE: load = PRG, type = ro, start = $C000;
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DATA: load = PRG, run = RAM, type = rw, define = yes;
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RODATA: load = PRG, type = ro;
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VECTORS: load = PRG, type = ro, start = $FFFA;
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}
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.ifndef HARDWARE_INC
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HARDWARE_INC = 1
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; CPU settings
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CPU_HZ = 1843200
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; Serial/ACIA addresses
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SERIAL_DATA = $8400
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SERIAL_STATUS = $8401
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SERIAL_COMMAND = $8402
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SERIAL_CONTROL = $8403
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; VIA addresses
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VIA_PORTB = $8000
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VIA_PORTA = $8001
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VIA_DDRB = $8002
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VIA_DDRA = $8003
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VIA_T1C_L = $8004
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VIA_T1C_H = $8005
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VIA_T1L_L = $8006
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VIA_T1L_H = $8007
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VIA_T2C_L = $8008
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VIA_T2C_H = $8009
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VIA_SR = $800a
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VIA_ACR = $800b
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VIA_PCR = $800c
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VIA_IFR = $800d
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VIA_IER = $800e
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VIA_PORTA_2 = $800f
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.endif
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; Serial port helper function
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; Serial is handled by the 65c51n (this thing has a few bugs)
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.export serial_setup, serial_recv_char, serial_print_char, serial_baud_19200, serial_baud_9600
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.include "hardware.inc"
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; -----------------------------
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; Active wait loop calculations
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; -----------------------------
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INNER_LOOP = 9 ; Inner loop count (sets granularity of the waiting period)
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; cycles per outer pass: ldx(2) + innerLoop(5*INNER_LOOP-1) + dey(2) + bne(3)
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PASS_CYC = INNER_LOOP * 5 + 6
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; passes for each 10bit frame (8N1), rounded up
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PASSES_19200 = (10 * CPU_HZ/19200 + PASS_CYC - 1) / PASS_CYC
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PASSES_9600 = (10 * CPU_HZ/9600 + PASS_CYC - 1) / PASS_CYC
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.assert PASSES_9600 < 256, error, "CPU clock too fast for this delay; raise INNER_LOOP"
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; ACIA control register presets: internal BAUD, 8N1
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SERIAL_CTRL_19200 = %00011111
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SERIAL_CTRL_9600 = %00011110
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; ||||````- 19200/9600 baud
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; |||`----- Receiver clock is baud rate
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; |``------ 8bit word
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; `-------- 1 stop bit
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; -----------------------------
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; -----------------------------
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.zeropage
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tx_passes: .res 1 ; Variable to store outer loop passes
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.code
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serial_setup:
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; 65c51n has a few bugs. check http://forum.6502.org/viewtopic.php?f=4&t=2543&start=30#p29795
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lda #$00
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sta SERIAL_STATUS ; Write to the status register for program reset
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lda #$0b ; %0000 1011
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sta SERIAL_COMMAND ; || |||`- Data terminal ready (DTRB low)
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; || ||`-- IRQB disabled
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; || ``--- RTSB low, transmit interrupt disabled
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; |`------ Receiver normal mode
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; `------- Parity disabled
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jsr serial_baud_19200
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rts
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serial_baud_19200:
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lda #SERIAL_CTRL_19200
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sta SERIAL_CONTROL
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lda #PASSES_19200
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sta tx_passes
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rts
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serial_baud_9600:
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lda #SERIAL_CTRL_9600
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sta SERIAL_CONTROL
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lda #PASSES_9600
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sta tx_passes
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rts
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serial_recv_char:
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lda SERIAL_STATUS ; read status
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and #$08 ; mask receive status flag
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beq serial_recv_char; if buffer is empty, loop
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lda SERIAL_DATA ; get byte
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rts
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serial_print_char:
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sta SERIAL_DATA ; send character
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;fall through to the delay routine
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serial_delay:
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phy ; save y reg
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phx ; save x register
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ldy tx_passes ; outer passes
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@ydelay:
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ldx #INNER_LOOP ; Init x register
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@xdelay: ; loop time was calculated above by the assembler
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dex ; decrement low index
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bne @xdelay ; loop back until x is 0
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dey ; decrement high
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bne @ydelay ; loop until y is 0
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@delay_done:
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plx ; return x
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ply ; return y
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rts
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.include "hardware.inc"
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+72
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.import serial_setup, serial_print_char, serial_recv_char
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.import copy_data
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; ---------------
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; ZP
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; ---------------
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.zeropage
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; Zero-page variables ($0000 - $00ff)
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; ---------------
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; BSS
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; ---------------
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.bss
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; RAM variables ($0200 - $7fff)
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; ---------------
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; DATA
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; ---------------
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.data
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; Initialized RAM variables ($0200 - $7fff)
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; ---------------
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; CODE
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; ---------------
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.code
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; Actual program code ($c000 - $fff9)
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reset: ; Program starts here
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; System setup
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sei ; disable interrupts while setting things up
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cld ; clear BCD mode flag (undefined on NMOS 6502, auto cleared on 65C02)
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ldx #$ff
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txs ; Reset stack pointer
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jsr copy_data ; copy data variables from ROM to RAM
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jsr serial_setup ; setup serial interface (65C51N). 19200 baud set as default
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print_hello_world:
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ldx #0
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@loop:
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lda str_hello_world,x ; get char
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beq @end ; IF char is 0, done
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jsr serial_print_char ; send char to console
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inx ; increment x (next char)
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jmp @loop
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@end:
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jmp @end
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irq_handler: ; IRQ Handler
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rti ; Do nothing
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nmi_handler: ; NMI handler
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rti ; Do nothing
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; ---------------
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; RODATA
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; ---------------
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.rodata
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; Constants
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str_hello_world: .asciiz "Hello, World!"
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; ---------------
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; VECTORS
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; ---------------
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.segment "VECTORS"
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; NMI, RESET and IRQ vectors
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.word nmi_handler
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.word reset
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.word irq_handler
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.import __DATA_LOAD__, __DATA_RUN__, __DATA_SIZE__
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.export copy_data
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.zeropage
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src: .res 2
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dst: .res 2
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.code
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copy_data:
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; Copy data segment from ROM to final RAM location
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lda #<__DATA_LOAD__ ; get source address low byte
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sta src
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lda #>__DATA_LOAD__ ; get source address high byte
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sta src+1
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lda #<__DATA_RUN__ ; get runtime final address low byte
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sta dst
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lda #>__DATA_RUN__ ; get runtime final address high byte
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sta dst+1
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ldx #>__DATA_SIZE__ ; number of 256 byte pages to copy (high byte)
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beq @tail ; if no full pages to copy, skip
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ldy #0
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@page:
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lda (src),y ; grab byte
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sta (dst),y ; store byte
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iny
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bne @page ; for 256 cycles
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inc src+1 ; increment source high byte (next memory page)
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inc dst+1 ; increment destination high byte (next memory page)
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dex ; decrement full pages counter
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bne @page ; if no more full pages, stop
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@tail: ; copy remaining non full page
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ldy #0
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cpy #<__DATA_SIZE__ ; check if there is data to copy
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beq @done ; if no data, done
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@byte:
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lda (src),y
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sta (dst),y
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iny
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cpy #<__DATA_SIZE__ ; when y == __DATA_SIZE__, done
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bne @byte ; else, continue
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@done:
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rts
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